2017학년도 제2차
대학교원 신규채용
접수기간: 2017.10.10. (화) ~ 10. 23. (월) 기간 중 월~금 10:00~17:00
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2017.10.19 17:00 302동 308호 Lift: a Functional Approach to Generating High Performance GPU Code using Rewrite Rules

Lift: a Functional Approach to Generating High Performance GPU Code using Rewrite Rules

Prof. Christophe Dubach, University of Edinburgh

Abstract: Graphic processors (GPUs) are the cornerstone of modern heterogeneous systems. GPUs exhibit tremendous computational power but are notoriously hard to program. High-level programming languages have been proposed to address this issue. However, they often rely on complex analysis in the compiler and device-specific implementations to achieve maximum performance. This means that compilers and software implementations need to be re-tuned for every new device.
In this talk, I will present Lift, a novel high-level data-parallel programming model. The language is based on a surprisingly small set of functional primitives which can be combined to define higher-level algorithmic patterns. A system of rewrite-rules is used to derive device-specific optimised low-level implementations of the algorithmic patterns. The rules encode both algorithmic choices and low-level optimisations in a unified system and let the compiler explore the optimisation space automatically. Preliminary results show this approach produces GPU code that matches the performance of highly tuned implementations of several computational kernels including linear algebra operations.

Speaker: Christophe Dubach received his Ph.D in Informatics from the University of Edinburgh in 2009 and holds a M.Sc. degree in Computer Science from EPFL (Switzerland). He is a Reader (Associate Professor) in the Institute for Computing Systems Architecture at the University of Edinburgh (UK). In 2010 he spent one year as a visiting researcher at the IBM Watson Research Center (USA) working on the LiquidMetal project. His current research interests includes high-level programming models for heterogeneous systems, co-design of both computer architecture and optimising compiler technology, adaptive microprocessor, and the application of machine learning in these areas.

Contact: Prof. Bernhard Egger, 02-880-1843

2017.10.17 11:00 301동 551호 SiLago: The Next Generation Synchorous VLSI Design Platform

SiLago: The Next Generation Synchorous VLSI Design Platform

Prof. Ahmed Hemani, Royal Institute of Technology, Sweden

Abstract: The VLSI community faces two challenges that we propose to address with the SiLago Method. The first problem is the unsustainably large engineering cost of VLSI design that is suffocating innovation and introduction of new product categories that requires orders of magnitude greater computational and silicon efficiencies that can only be achieved by custom hardware design. This recipe goes against the current state-of-the-practice, the software centric accelerator rich platform based design style that has not only failed to reduce the engineering cost but also delivers sub-optimal designs and does not scale with technology trends.
As a solution, we propose raising the abstraction of physical design platform from the present day boolean level standard cells to micro-architectural level SiLago (Silicon Large Grain Objects) blocks as the atomic physical design building blocks and introduce a grid based synchorous VLSI Design scheme discipline to compose arbitrary designs by abutting SiLago blocks to eliminate the logic and physical syntheses for the end user. Synchorous is derived from the Greek word for space – choros. Synchorous objects discretize space uniformly with the grid, the way synchronous objects discretize time with clock ticks.
We call this the SiLago method and show that it provides 2-3 orders more efficient synthesis from application level compared to the standard cell based commercial design flows with a modest loss in design quality.

Speaker: Ahmed Hemani is Professor in Electronic Systems Design at School of ICT, KTH, Kista, Sweden. His current areas of research interests are massively parallel architectures and design methods and their applications to scientific computing and autonomous embedded systems inspired by brain. In past he has contributed to high-level synthesis – his doctoral thesis was the basis for the first high-level synthesis product introduced by Cadence called visual architect. He has also pioneered the Networks-on-chip concept and has contributed to clocking and low power architectures and design methods. He has extensively worked in industry including National Semiconductors, ABB, Ericsson, Philips Semiconductors, Newlogic.

Contact: Prof. Bernhard Egger, 02-880-1843

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