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일시 : 2017년 12월 8일(금) | 장소 : 서울대학교 글로벌공학교육센터 5층
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세미나 일정표
날짜 시간 장소 제목
2017.11.03 11:00 302-209-1 Exascale Beyond: Computing in the Day After Tomorrow

세미나 이름

Exascale Beyond: Computing in the Day After Tomorrow

제목

Exascale Beyond: Computing in the Day After Tomorrow

발표자

Brian J. d'Auriol

발표자 소속


세미나 시간

11:00 - 12:00

세미나 장소

302-209-1

호스트

Prof. Bernhard Egger

발표내용

Exascale computing represents the next supercomputing milestone which is expected to be achieved by 2019/20. Much of the present-day petascale computing relies on commodity components augmented by hardware accelerators and fast message-passing networks some of which may incorporate opto-electronic components; but such may not scale up to support faster computing environments. In the near future, computing technologies based on present-day supercomputing vendor development infrastructures augmented by intensive research and development of all aspects of an exascale computing ecosystem are under development for deployment aimed at computational intensive applications. Yet, convergence technologies such as optical and nano-optical are rapidly maturing and are poised to offer exciting alternatives by the next decade. At the same time, new types of big data information stream-based applications will need to be supported as information societies continue to grow and expand. This talk introduces the OLARPBS exascale bandwidth all-optical parallel computing model as a viable alternative to support exascale and beyond computing in the next decade with specific applications to big data information stream-based applications. Unique features of this model include the elimination of the traditional separation of computational and communication phases thereby also eliminating issues with message-passing, optical registers as the primary data storage memory thereby also introducing both spatial and temporal positioning of data, reconfigurable interconnections thereby also increasing flexibility while decreasing latency of communications and intrinsic physical layout geometries. Architecture, organization, operative aspects, algorithm design and performance along with future research and development requirements of this novel model for the future are discussed in this talk.

발표자 소개

Brian J. d'Auriol received the BSc(CS) and Ph.D. degrees from the University of New Brunswick (Canada) in 1988 and 1995, respectively. He has held various research and professorial appointments and positions in the U.S. (Universities of Texas at El Paso, Akron, and Wright State), Canada (Universities of Manitoba and New Brunswick), and Korea (SUNY, Kyung Hee University) and published over 90 peer-reviewed papers in international journals and conferences. His research is described as visual enabled computing and includes: insightful serviceable visualizations aimed at understanding and knowledge, via learning, insight, impression and emotion to facilitate creativity and decision-making; exascale and beyond bandwidth optical conduit-based parallel computing; and design of a personal visualization assistant which is a big data application.

문의

Prof. Bernhard Egger (880-1843)
2017.11.13 11:00 302동 308호 Understanding and Improving the Latency of DRAM-Based Memory Systems

세미나 이름

SNU CSE Seminar

제목

Understanding and Improving the Latency of DRAM-Based Memory Systems

발표자

Dr. Kevin Chang

발표자 소속

Carnegie Mellon University

세미나 시간

11:00~12:00

세미나 장소

302동 308호

호스트

유승주 교수님

발표내용

Over the past two decades, the storage capacity and access bandwidth of main memory have improved tremendously, by 128x and 20x, respectively. These improvements are mainly due to the continuous technology scaling of DRAM (dynamic random-access memory), which has been used as the physical substrate for main memory. In stark contrast with capacity and bandwidth, DRAM latency has remained almost constant, reducing by only 1.3x in the same time frame. Therefore, long DRAM latency continues to be a critical performance bottleneck in modern systems. Increasing core counts, and the emergence of increasingly more data-intensive and latency-critical applications further stress the importance of providing low-latency memory accesses.

In this talk, we will identify three main problems that contribute significantly to long latency of DRAM accesses. To address these problems, we show that (1) augmenting DRAM chip architecture with simple and low-cost features, and (2) developing a better understanding of manufactured DRAM chips together leads to significant memory latency reduction. Our new proposals significantly improve both system performance and energy efficiency.

발표자 소개

Kevin Chang is a recent Ph.D. graduate in electrical and computer engineering from Carnegie Mellon University, where he's advised by Prof. Onur Mutlu. He is broadly interested in computer architecture, large-scale systems, and emerging technologies. Specifically, his graduate research focuses on improving performance and energy-efficiency of memory systems. He will join Facebook as a research scientist. He was a recipient of the SRC and Intel fellowship.

문의

880-9392
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