SNU Prof. Jaehyouk Choi Team Wins Top Paper Award at ISSCC, the “Olympics of Semiconductor Design”
- Innovative design reduces power consumption of HBM clock distribution circuits to less than one-tenth
- Elected as the single most impactful paper among 165 Asia-Pacific submissions


▲ (From left) Prof. Jaehyouk Choi, ISSCC Chair Edith Beigné, researcher Jeongbeom Seo, researcher Yuhwan Shin

Seoul National University College of Engineering announced that a research team led by Prof. Jaehyouk Choi of the Department of Electrical and Computer Engineering (Jeongbeom Seo, Yoonseo Cho, Yuhwan Shin, and Jaehyouk Choi) received the “ISSCC 2025 Takuo Sugano Award,” the top paper award, at the International Solid-State Circuits Conference (ISSCC) 2026, held on February 16 in San Francisco, USA.

Organized by the Institute of Electrical and Electronics Engineers (IEEE), ISSCC was established in 1954 and marked its 73rd edition this year. It is the world’s largest and most prestigious international conference in semiconductor integrated circuit design. Each year, cutting-edge semiconductor technologies from global companies and universities are unveiled for the first time at the conference, earning it the nickname “the Olympics of semiconductor design.”

The Takuo Sugano Award is the most prestigious paper award presented at ISSCC. It is given annually to a single paper from the Asia-Pacific region that demonstrates not only outstanding technical excellence but also significant academic and industrial impact. At ISSCC 2025, a total of 165 papers from the Asia-Pacific region were presented.

This achievement marks the first time in 20 years that an SNU research team has received the award, following a previous win at ISSCC 2005. It is regarded as a significant milestone that once again demonstrates the global competitiveness of Korea’s semiconductor circuit design research.

The award-winning paper, titled “An 850μW 2-to-5GHz Jitter-Filtering and Instant-Toggling Injection-Locked Quadrature-Clock Generator for Low-Power Clock Distribution in HBM Interfaces,” presents a novel circuit design technique that can fundamentally address the critical challenges of power consumption and heat generation in high-bandwidth memory (HBM), a key semiconductor technology for AI systems.

Modern HBM systems must simultaneously operate more than 2,000 data input/output channels to enable ultra-high-speed data transfer between GPUs and memory. In this process, distributing multi-phase high-frequency signals in the gigahertz (GHz) range consumes a substantial amount of power, which has been identified as a primary cause of heat generation in HBM.

To address this issue, Prof. Choi’s team proposed a new architecture that replaces the conventional parallel distribution of high-frequency multi-phase signals. Instead, their approach serially transmits phase information through a single low-frequency signal and reconstructs it just before data input/output. Through this innovation, the team successfully reduced power consumption to less than one-tenth of that required by conventional methods.

Jeongbeom Seo, a doctoral researcher and first author of the paper, said, “I am very pleased to have developed a technology that can make a practical contribution to the advancement of HBM, a core component of Korea’s semiconductor industry. Moving forward, I will continue my research with a strong sense of responsibility to further strengthen the global competitiveness of Korea’s semiconductor industry amid intense international competition.”

▲ (From left) researcher Jeongbeom Seo, researcher Yoonseo Cho, researcher Yuhwan Shin, Prof. Jaehyouk Choi


▲ Photo of the Takuo Sugano Award plaque

[Contact Information]

Jeongbeom Seo, Ph.D. Candidate, Integrated Circuits and Systems Laboratory, Department of Electrical and Computer Engineering, Seoul National University / jeongbeom1@snu.ac.kr